On this page, I will show some of the scientific highlights and market insights on which I have been working on in recent years. With the following list of contents, you will be able to jump quickly to the topic you may be interested in:
- 2D interference lightswitch arrays for structured illumination (3D measurements)
- Choosing the right waveguide material
- Photonics sensing at wafer scale
- Chip / Micro Transfer Printing
- Optical switches for wafer integration
- What are PICs?
- Co-packaged optics for increasing data transfer rates
- Cryo-CMOS
Optical interference switches for structured illumination (PhD thesis, 2006, IMSAS University of Bremen, Germany)
In my PhD studies, together with my outstanding team, I have successfully completed two scientific projects: MicroEnd (German BMBF) and HydroSurf (EU). The first was to develop and manufacture small, mostly translucent displays (or better said: 2D lightswitch arrays) in non-medical endoscopes for achieving structured illumination of hidden parts e.g. in Automotive or avionics. The latter was to develop a gas-phase hydrophobisation process for avoiding in-use stiction of small membranes, which was necessary to stabilize the membranes of the lightswitch array.
Think, for instance, about the inward 3D inspection & measurement of an aircraft wing, whether cracks or other topologically visible damage are showing up on the surface inside. By measuring the deformation of the well-known, projected pattern on the surface by using a triangulation algorithm, one is able to determine surface topology in the sub-millimeter range. This means, this technique is used for broad areas, typically > 1m². The design, calculation and simulation of interference behaviours, switch array manufacturing, and testing of these displays are briefly explained below (coming soon). For more information, please have a look at my thesis (German).
More information on actual developments in the field of optical switches can be found in the section Optical switches for wafer integration.
Choosing the Right Waveguide Material — A Comparative Overview for Photonics & Microelectronics
Photonic Circuits (PICs) are gaining more and more interest since light signal promis higher bandwidths and lower energy consumption for future demands for high data transfer in KI and HPC, and also for Quantum Computing. Whether you’re designing compact photonic circuits or optimizing high-speed optical communication, the material choice for waveguides shapes everything from performance to scalability. I’ve compiled a comparative snapshot of some widely used materials — from Lithium Niobate to Gallium Arsenide — across key metrics: refractive index, losses, fabrication processes, and application-specific pros and cons.
Here’s a quick guide to help researchers, designers, and photonic engineers navigate this complex landscape more confidently.
Waveguides on a wafer (c) Schott.
Summary:
There’s no one-size-fits-all when it comes to waveguide materials. High-index contrast (e.g., a-Si, GaAs) offers tighter confinement but often at the cost of absorption. Materials like Si₃N₄ and Al₂O₃ strike a balance between performance and CMOS-compatibility. For high-speed electro-optic modulation, lithium niobate (LiNbO₃) continues to shine. The right choice ultimately depends on your application bandwidth, integration needs, and fabrication constraints.
Photonics at the wafer scale: sensing the future of AI, quantum, and communication.
As we push the boundaries of data transmission, quantum computing, and AI, the need for scalable, high-performance photonic sensors becomes ever more critical. Whether detecting single photons or enabling ultra-fast optical links, these sensors must not only be sensitive and fast: They must also be integrable at the wafer level to meet the demands of modern chip-scale systems.
Many of these sensor types, including SPADs and SNSPDs, have already demonstrated successful wafer-level integration using CMOS-compatible or hybrid photonic platforms. This enables co-integration with electronics and scalable manufacturing.
The table below shows a selection of state-of-the-art photonic sensor types, each evaluated by operational wavelength, sensitivity, and their respective advantages and drawbacks, with an emphasis on scalability and compatibility with wafer-level integration.
Thus, SPADs and APDs are widely used in classical optical communication and imaging, offering CMOS compatibility and fast response, though their sensitivity and dark count rates vary by material. However, cryo environments may reduce dark counts drastically. SNSPDs and TES detectors are foundational to quantum photonics, achieving single-photon sensitivity and near-perfect quantum efficiency, albeit at the cost of cryogenic cooling and complex packaging. These may apply when cryo conditions are required anyway, e.g. for noise mitigation, like in superconductive or in ion trap based QC. Emerging concepts like QD-based detectors and BSI CMOS sensors promise novel trade-offs between integration, cost, and performance, though many are still at experimental stages or limited to specific spectral bands.
Conclusion: Photonic sensor integration at wafer scale has made significant progress — SPADs and APDs lead in scalability, while superconducting sensors define the gold standard for quantum-level detection. However, bridging this gap remains a key research challenge: achieving room-temperature, high-efficiency, low-noise detectors that are CMOS-compatible and scalable. This will be essential for enabling integrated photonic systems in quantum computing, neuromorphic AI, and high-speed optical links, at scale, and in silicon.
Smart Chips on the Move: An Introduction to Transfer Printing in Microelectronics.
In microelectronics and flexible systems integration, chip or micro transfer printing is reshaping how we detach and reposition micro-scale devices—precisely, reliably, and often in large arrays.
From solid silicon to stretchable foils, substrates vary widely, like different materials, substrate shapes and sizes, crystalline orientations, like <100> vs. <111>, and CMOS/non-CMOS and SOI (which is often used as a source/release wafer).
This means: Once agreed on a few design features like chip sizes and electric interfaces (bond pads, wafer bumps, etc.), source and device wafers can be fabricated at completely different locations with different processing capabilities!! – This is a marvelous synergy effect, a win-win for two or more parties previously working alone with limited processing capabilities.
Many different printable microscale devices have already been realized, including lasers, LEDs, solar cells, and integrated circuits in a wide variety of IC materials, including silicon, GaAs, InP, GaN, and thin-film dielectrics, including diamond. The aims are to maximize production flexibility, scalability, and functionality across sensing, displays, and data transmission.
Not all transfer methods are created equal and suited for all applications. Since elastomeric stamping may be the most mature and widely used method, others like laser-assisted processes are also emerging techniques and are different concerning their precision, scalability, and compatibility.
Comparison of common transfer methods: See Tab. 1 for details.
Some of the most prominent key applications include:
☑️ Flexible electronics & wearables
☑️ Heterogeneous system integration
☑️ Advanced packaging
☑️ Biomedical sensors
☑️ Transparent displays
Who’s shaping the future? See Tab. 2 for the leading contributors.
These are just a few highlights. Products using this versatile technology are already hitting the market. The future of electronics might well be printed—chip by chip
Optical switches for wafer integration
As data volumes increase drastically and latency demands tighten, the role of optical switches in next-generation communication infrastructures is a topic of intense research and improvement. These devices allow for the dynamic routing of optical signals without converting them into electrical form. This will preserve speed, reduce power consumption, and minimize bottlenecks.
Optical switches differ widely not only in architecture, switching speed, and maturity, but also in their operating wavelength ranges, which strongly impact their suitability for telecom, data center, sensing, and quantum applications. Understanding these differences is essential for designing scalable, resilient photonic networks.
The table below shows the current Optical Switch landscape and highlights key optical switch types, providing a snapshot of their underlying principles, industry adoption, and performance metrics. It offers decision-makers and researchers a quick reference to assess suitability across application scenarios ranging from data center networking to quantum photonics.
While commercial-grade mechanical and MEMS switches are widely deployed, solid-state and quantum-grade switches remain in quite early development and/or do not meet high-demanding specs. However, since structures with non-moving parts offer some main advantages like less sensitivity to shock and humidity, it is advised to move things further here.
Key challenges include:
- Reducing insertion loss in waveguide-based switches
- Improving switching precision and scalability for quantum applications
- Minimizing polarization-dependent loss and crosstalk
- Enhancing environmental robustness for industrial deployment
To accelerate progress, collaboration between photonics researchers, semiconductor manufacturers, and AI-driven control systems is essential. Standardization efforts (e.g., IEEE 802.3cd) and third-party reliability certifications (e.g., Telcordia GR-1221) will play a pivotal role in bridging lab innovation to field deployment.
For reference and getting a broader picture, also have a look at my former posts (links in first comment).
Advancing photonic switch technologies demands cross-disciplinary collaboration—let’s foster dialogue, just contact me for further discussion!
What are PICs?
From quantum sensing to satellite communications, photonic integration is no longer a niche—it’s becoming a cornerstone of next-generation system design.
As digital infrastructures evolve and data traffic continues to surge, the demand for faster, more efficient, and energy-conscious components becomes critical. Photonic Integrated Circuits (PICs) present a disruptive alternative or supplement to conventional CMOS-based electronics by leveraging light—rather than electrical charge—to transmit and process information.
Built on optical waveguides, beam splitters, modulators, and detectors, PICs integrate multiple photonic functions on a single chip. They are already powering:
- High-speed fiber and satellite-based telecommunications
- Spaceborne optical links and inter-satellite communication
- Quantum computing and quantum sensing
- LiDAR and optical gyroscopes for autonomous vehicles
- Medical diagnostics and biosensing
- Industrial monitoring and structural health sensing
Depending on the transmission distance, PICs are deployed in different components and subsystems – see the first table below.
With benefits like up to 10× higher bandwidth and up to 100× lower energy per bit compared to traditional copper-based interconnects, PICs are poised to reshape the semiconductor industry.
The second table provides a side-by-side comparison of core CMOS components and their photonic counterparts.
Summary: The last table proves: PICs won’t fully replace CMOS, but they will enhance and redefine system architectures where light beats electrons.
Interested? Just contact me for further discussions— I’ll be happy to explore this future together with you!
Co-packaged optics for increasing data transfer rates
As data rates surge and AI workloads grow more complex, traditional electrical interconnects are reaching their physical limits. Signal loss, energy inefficiency, and thermal challenges are bottlenecking performance — especially in high-density data centers and next-gen AI clusters.
Just look at the data explosion in the graph below: From just 2 zettabytes in 2010 to a projected 181 zettabytes in 2025 — the way we move data must evolve. This is where Co-Packaged Optics (CPO) steps in.
By integrating optical transceivers directly next to switch ASICs, CPO shortens electrical paths, reduces power consumption, and unlocks ultra-high bandwidths. It’s a fundamental rethinking of how data is moved — not across racks, but inside packages.
Why it matters:
✅ Enables 1.6T+ Ethernet and beyond
✅ Reduces SerDes power overhead
✅ Critical for scalable LLM and HPC architectures
✅ Aligned with silicon photonics and chiplet trends
Cryo-CMOS
What is Cryo-CMOS? Enabling Scalable Electronics at Millikelvin Temperatures.
As quantum computing, deep-space sensing, and fundamental physics demand ultra-low-noise electronics, Cryogenic CMOS (Cryo-CMOS) is emerging as a key building block. Designed to function from 4 K down to below 100 mK, Cryo-CMOS circuits combine the advantages of CMOS scaling with cryogenic efficiency.
Where Cryo-CMOS is making an impact:
– Quantum computing: qubit control, multiplexed readout near dilution refrigerators
– Space exploration: infrared detectors, low-noise front-ends for deep space missions
– Scientific instrumentation: MRI systems, dark matter experiments, superconducting logic
Current research explores state-of-the-art nodes (14 nm and below) with cryo-optimized design kits and device architectures, including:
☑️ Modified transistor models (e.g. threshold shifts, subthreshold slope)
☑️ High-k dielectrics and SOI substrates
☑️ HEMTs for cryogenic amplification
☑️ Cryo-aware cell libraries and layout constraints
☑️ Cryo-compatible interconnects and backend stacks
However, one key engineering challenge dominates:
Thermal mismatch between materials, such as silicon, oxides, and metals, leads to mechanical stress and functional instability during cooldown. Without mitigation, device mismatch and reliability issues can compromise performance. The table below shows some of these and similar effects and a choice of mitigation strategies.
The Pelgrom-aware design refers to layout strategies that minimize mismatch between nominally identical devices, especially transistors, by taking into account the statistical variations described in the Pelgrom model. This model shows that device mismatch is inversely proportional to the square root of the transistor area.
In practice, Pelgrom-aware layouts use:
✅ Matched geometry and orientation
✅ Common-centroid or interdigitated transistor placement
✅ Dummy devices to shield edge effects
✅ Symmetry to reduce gradient sensitivity
In cryogenic CMOS design, this approach becomes even more important. At low temperatures, process-induced mismatches and mechanical stress can significantly degrade performance. Pelgrom-aware techniques help stabilize circuit behavior across cooldown cycles and enable higher yield in precision analog and mixed-signal blocks.
Studies show that leakage currents can drop by over five orders of magnitude at 10 K, while drive performance remains stable—an ideal setup for ultra-low-power cryogenic logic.
Summary: Cryo-CMOS enables scalable, low-noise electronics where conventional CMOS fails. But tackling thermal mismatch is essential to build robust platforms that operate reliably below 4 K.
